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QS532806/A GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
FEATURES:
- - - - - - - - JEDEC compatible LVTTL level 10 low skew clock outputs Monitor output Clock inputs are 5V tolerant Pinout and function compatible with QS5806 25 on-chip resistors for low noise Input hysteresis for better noise margin Guaranteed low skew: * 0.7ns output skew (same bank) * 0.9ns output skew (different bank) * 1ns part-to-part skew Std. and A speed grades Available in QSOP and SOIC packages
QS532806/A
DESCRIPTION
The QS532806 clock driver/buffer circuit can be used for clock buffering schemes where low skew is a key parameter. The QS532806 offers two banks of five inverting outputs. Designed in IDT's proprietary CMOS process, these devices provide low propagation delay buffering with onchip skew of 0.7ns for same-transition, same-bank signals. The QS532806 has on-chip series termination resistors for lower noise clock signals. The series resistor versions are recommended for driving unterminated lines with capacitive loading and other noise sensitive clock distribution circuits. These clock buffer products are designed for use in high-performance workstations, embedded and personal computing systems. Several devices can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks.
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FUNCTIONAL BLOCK DIAGRAM
O EA 5
INA
O A5 - O A1
MO N 5 O B5 - O B1
INB
O EB
INDUSTRIAL TEMPERATURE RANGE
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c 1999 Integrated Device Technology, Inc.
SEPTEMBER 2000
DSC-5783/-
QS532806/A GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
VCCA OA1 OA2 OA3 GNDA OA4 OA5 GNDQ OEA IN A 1 2 3 4 5 6 7 8 9 10 20 19 18 17 SO 20-2 16 SO 20-8 15 14 13 12 11 VCCB O B1 O B2 O B3 G NDB O B4 O B5 MON O EB IN B
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) VAC IOUT TSTG TJ Description Supply Voltage to Ground DC Output Voltage VOUT DC Input Voltage VIN AC Input Voltage (pulse width 20ns) DC Output Current VIN < 0 DC Output Current Max. Sink Current/Pin Storage Temperature Junction Temperature
(1) Unit V V V V mA mA C C
Max. - 0.5 to +7 - 0.5 to Vcc+0.5 - 0.5 to +7 -3 -20 120 - 65 to +150 150
QSOP/ SOIC TOP VIEW
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc Terminals. 3. All terminals except Vcc.
CAPACITANCE
(TA = +25OC, f = 1.0MHz, VIN = 0V, VOUT = 0V)
QSOP Pins All Pins Typ. 4 Max. (1) 6 SOIC Typ. 5 Max. (1) 7 Unit pF
NOTE: 1. This parameter is guaranteed but not production tested.
PIN DESCRIPTION
Pin Names OEA, OEB INA, INB OAn, OBn MON I/O I I O O Description Output Enable Inputs Clock Inputs Clock Outputs Monitor Outputs (non-disable)
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QS532806/A GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 3.3V 0.3V
Symbol VIH VIL VIC VOH VOL Parameter Input HIGH Voltage Input LOW Voltage Clamp Diode Voltage (3) Output HIGH Voltage Output LOW Voltage Test Conditions Guaranteed Logic HIGH for Inputs Guaranteed Logic LOW for Inputs Vcc = Min., IIN = -18mA Vcc = Min., IOH = -100A Vcc = Min., IOH = -8mA Vcc = Min., IOL = 100A Vcc = Min., IOL = 6mA Vcc = Min., IOL = 8mA IIN IOZ IOFF IODH IODL IOS ROUT Input Leakage Current Output Leakage Current Input Power Off Leakage Output HIGH Current (2) Output LOW Current (2) Short Circuit Current Output Resistance
(2,3) (4)
Min. 2 -0.5 -- Vcc - 0.2 2.4 -- -- -- -- -- -- -30 30
Typ.(1) -- -- -0.7 -- -- -- -- -- -- -- -- -100 100 -- 28
Max. 5.5 0.8 -1.2 -- -- 0.2 0.4 0.5 1 1 1 -200 200 -- --
Unit V V V V V V V V A A A mA mA mA
Vcc = Max., VIN = Vcc or GND Vcc = Max., VOUT = Vcc or GND Vcc = 0V, VIN = Vcc or GND Vcc = 3.3V, VIN = VIH or VIL, VO = 1.5V Vcc = 3.3V, VIN = VIH or VIL, VO = 1.5V Vcc = Max., VOUT = GND Vcc = Min
- 60
--
NOTES: 1. Typical values are at VCC = 3.3V, TA = 25C. 2. Not more than one output should be used to test this high power condition. Duration is less than one second. 3. Guaranteed by design but not tested. 4. Output resistance represents the total output impedence of the logic device and includes added series termination resistance.
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICC ICCD IC Parameter Quiescent Power Supply Current Supply Current per Input HIGH Dynamic Power Supply Current per Output (2) Total Power Supply Current Examples (2,4) Test Conditions (1) VCC = Max., VIN = GND or Vcc VCC = Max., VIN = 3V VCC = Max., OEA = OEB = GND Outputs Toggling at 50% duty cycle VCC = Max., VIN = GND or Vcc OEA = OEB = GND 50% duty cycle, fI = 10MHz VIN = GND or 3V five outputs VCC = Max., VIN = GND or Vcc OEA = OEB = GND 50% duty cycle, fI = 2.5MHz VIN = GND or 3V All outputs toggling Typ. (3) 0.01 0.1 65 3.5 3.5 1.8 1.8 Max. 100 30 100 5.2 5.2 2.9 2.9 Unit A A A/MHz mA mA mA mA
NOTES: 1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics. 2. Guaranteed by design but not tested. CL = 0pF. 3. Typical values are for reference only. Conditions are VCC = 3.3V, TA = 25C. 4. IC = ICC + (ICC)(DH)(NT) + ICCD (fO)(NO) where: DH = Input Duty Cycle NT = Number of TTL HIGH inputs at DH (one or two) fO = Output Frequency NO = Number of outputs at fO (five or ten)
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QS532806/A GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
SKEW CHARACTERISTICS OVER OPERATING RANGE
TA = -40C to +85C, VCC = 3.3V 0.3V CLOAD = 50pF (no resistor)
QS532806 Symbol tSK(01) tSK(02) tSK(P) tSK(T) Parameter (1) Skew between all outputs, same transition, same bank Skew between two outputs, same transition, different banks Pulse Skew; skew between opposite transitions of the same output (tPHL - tPLH) Part-to-part skew (2) Min. -- -- -- -- Max. 0.7 0.9 1.4 1.5 QS532806A Min. -- -- -- -- Max. 0.7 0.9 1.4 1 Unit
ns ns ns ns
NOTES: 1. This parameter is guaranteed but not production tested. Skew parameters apply to propagation delays only. 2. tSK(T) only applies to devices of the same transition, part type, temperature, power supply voltage, loading package, and speed grade.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
TA = -40C to +85C, VCC = 3.3V 0.3V CLOAD = 50pF (no resistor)
QS53806 Symbol tPLH tPHL tR tF tPZL tPZH tPLZ tPZH Parameter (1) Propagation Delay (2) Output Rise Time, 0.8V to 2V (3) Output Fall Time, 2V to 0.8V (3) Min. 1.5 -- -- 1.5 1.5 Max. 6.5 2 2 8 7 Min. 1.5 -- -- 1.5 1.5 QS532806A Max. 5.8 2 2 8 7 Unit
ns ns ns ns ns
Output Enable Time Output Disable Time
NOTES: 1. Minimums guaranteed but not production tested. 2. The propagation delay other range indicated by Min. and Max. specifications results from process and environmental variables. These propagation delays do not imply limit skew. 3. This parameter is guaranteed but not production tested.
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QS532806/A GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
Parameter Tested
Switch Position
tPLZ, tPZL All Others VCC VIN Pulse Generator 50 DUT 50pF 500 VOUT 500
Closed Open
6.0 V
Pulse generator for all pulses: f 1.0MHz; tF 2.5ns; tR 2.5ns
3V INPUT tPLH tPHL VOH 2.0V 1.5V 0.8V VOL tR tF tPLH OUPUT tPHL VOH 1.5V VOL tSK(p) = tPHL - tPLH 1.5V 0V INPUT 3V 1.5V 0V
OUPUT
PROPAGATION DELAY
PULSE SKEW -- tSK(P)
3V 3V INPUT tPLHA VOH tPHLA 1.5V 0V VOH OUPUT A 1.5V VOL tSK(02) OUPUT B tSK(02) VOH 1.5V VOL tPLHB tPHLB
INPUT tPLH1 tPHL1
1.5V 0V
OUPUT 1
1.5V VOL tSK(01) tSK(01) VOH 1.5V VOL tPLH2 tPHL2 tSK(01) = tPLH2 - tPLH1 or tPHL2 - tPHL1
OUPUT 2
tSK(02) = tPLHB - tPLHA or tPHLB - tPHLA
OUTPUT SKEW (SAME BANK) -- tSK(O1)
OUPUT SKEW (DIFFERENT BANKS) -- tSK(O2)
ENABLE CONTROL INPUT tPZL OUTPUT NORM ALLY LOW SWITCH CLOSED tPZH OUTPUT NORMALLY HIG H SWITCH OPEN 1.5V
DISABLE 3V 1.5V 0V tPLZ 3V 1.5V 0.3V VOL tPHZ 0.3V VOH PART 2 O UTPUT tSK(t) tSK(t) PART 1 O UTPUT INPUT tPLH1 tPHL1 3V 1.5V 0V VOH 1.5V VOL VOH 1.5V VOL 0V tPLH2 tPHL2
tSK(t) = tPLH2 - tPLH1 or tPHL2 - tPHL1
ENABLE AND DISABLE TIMES 5
PART-TO-PART SKEW -- tSK(T)
QS532806/A GUARANTEED LOW SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
QS XXXXX Device Type XX Package
Q SO
Quarter Size Small Outline Pacakge (SO20-8) Small Outline IC (SO20-2)
532806 Guaranteed Low Skew 3.3V CMOS Clock Driver/Buffer 532806A
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
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*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. The IDT logo, QuickSwitch, and SynchroSwitch are registered trademarks of Integrated Device Technology, Inc.
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